The present invention relates to a semiconductor device manufacturing method. In particular, the present invention relates to a method for forming an element-separation area on an SOI ("Silicon On Insulator") wafer.
Conventional methods for separating elements in semiconductor integrated circuits include the LOCOS ("Local Oxidation of Silicon") method, which uses thick oxidized films. In recent years, however, trench-mold separation methods have frequently been used to separate semiconductor elements in an SOI wafer. An SOI wafer comprises a support substrate and a silicon element substrate, attached together via an insulating film (hence "silicon on insulator"). In a conventional trench-mold separation method, a trench is formed that extends from the surface of the silicon element substrate down to the insulating film. Then an insulating film or, alternatively, both an insulating film and a polycrystal silicon film are buried in the trench. These trench-mold separation methods are suitable for use with high voltage-resistant elements, because the potentials of the elements can be perfectly isolated.
FIGS. 6(a) to 6(e) are cross-sectional views showing the manufacture of a semiconductor by a conventional trench-mold separation method. An SOI wafer comprises a silicon element substrate 3 adhering to a supporting substrate 1 via a separating insulating film 2. An oxidized film 4 is formed on the surface of silicon element substrate 2 [FIG. 6(a)]. Patterning and etching are then performed, using a photo-etching technique. Silicon element substrate 3 is etched down to separating insulating film 2, using patterned oxidized insulating film 4 as a mask, to form a trench 8 [FIG. 6(b)].
After removing the photo resist and oxidized insulating film 4 from silicon element substrate 3, an oxidized film 9 is formed on the surface of silicon element substrate 3 and on the side wall of trench 8 by thermal oxidation [FIG. 6(c)]. The thickness of oxidized film 9 is generally about 0.5-1.0 .mu.m. Low-pressure chemical vapor deposition (hereinafter "CVD") is subsequently used to deposit 2 .mu.m of a polysilicon film 5A on semiconductor element substrate 3 and in trench 8 [FIG. 6(d)]. Etchback is then performed to remove polysilicon film 5A from silicon element substrate 3 and the upper part of trench 8 while leaving the remainder of polysilicon film 5A in trench 8 [FIG. 6(e)].
The conventional trench-mold method employs thermal oxidization to form oxidized film 9. Since oxidized film 9 is used for insulation, it must have a thickness of at least about 0.5 .mu.m in order to obtain a high-voltage-resistant element. To obtain a film of the desired thickness, thermal oxidization must be executed at high temperatures over long periods of time. As a result, stress concentration may occur in corners 10, 11 of trench 8 and lead to deformation and degradation of crystals in corners 10, 11. This stress concentration probably is due to the difference in the thermal expansion coefficients of silicon element substrate 3 and oxidized film 9. As a result, the breakdown voltage of a semiconductor device formed on silicon element substrate 3 is weakened, and current leaks are more likely to occur.
To prevent these undesirable side effects, a semiconductor element may be separated from trench 8 and corners 10, 11 of the trench rounded off, as described in Japanese Laid Open Patent Application No. 129854/1991. However, if the semiconductor element is separated from trench 8, the size of the chip must be increased. In addition, although it is technically possible to round off corners 10, 11 of trench 8, uniformly etching the top and bottom of trench 8 becomes more and more difficult as the depth of trench 8 increases, and the probability of non-uniform roundness may increase. As a result, the breakdown voltage of the semiconductor devices may decrease, and current leaks therefrom will be nonuniform.